1. Field of the Invention
The present invention relates to a semiconductor device, and a method of producing the same. More particularly, it relates to a trench isolation structure for electrically isolating semiconductor elements.
2. Description of the Related Art
Trench isolation structure formed between semiconductor elements such as transistors has been becoming increasingly important as semiconductor devices are packaged with higher density and higher performance.
A method of producing trench isolation structure of the prior art used in the conventional semiconductor device will be described below with reference to FIGS. 12 through 21.
FIGS. 12 through 21 are cross sectional views showing first through tenth steps of the method of producing a trench isolation structure of the prior art.
First, referring to FIG. 12, a silicon oxide film 2 having thickness of 100 xc3x85 is grown on a principal plane of a P-type silicon substrate 1 by thermal oxidation process, followed by the deposition of a silicon nitride film 3 having thickness of 500 xc3x85 by low pressure CVD (Chemical Vapor Deposition) process and application of a resist to form a desired resist pattern 4 by photolithography technology.
After etching the silicon nitride film 3 and the silicon oxide film 2 with the resist pattern 4 used as a mask, the silicon substrate 1 is etched thereby to form a groove 5 having a depth of 4000 xc3x85 from the surface, and the resist pattern 4 is removed, as shown in FIG. 13.
Now referring to FIG. 14, where thermal oxidation is applied to the inner surface of the groove 5 formed in the silicon substrate 1, thereby to form a silicon oxide film 6 having thickness of 500 xc3x85.
Then as shown in FIG. 15, the groove 5 is filled up by depositing a silicon oxide filling 7 to a depth of 6000 xc3x85 by CVD process. Surface of the silicon oxide filling 7 is smoothed by CMP (Chemical Mechanical Polishing) process.
Now referring to FIG. 16, where the silicon nitride film 3 is selectively removed by using thermal phosphoric acid, thus forming a trench isolation structure 30 comprising the groove 5, the silicon oxide film 6 and the silicon oxide filling 7.
After the isolation trench 30 has been formed as shown in FIG. 17, boron ions are implanted with a density of 3xc3x971012/cm2 and an energy of 200 KeV by ion implantation process, thereby to form a channel stopper layer 35.
Now referring to FIG. 18, where the silicon oxide film 2 is removed by using hydrofluoric acid (HF) solution.
Now referring to FIG. 19, where a silicon oxide film having thickness of 50 xc3x85 which would become a gate oxidation film 8 of a transistor is formed by thermal oxidation process, and phosphorus-doped polycrystal silicon is deposited to a thickness of about 3000 xc3x85 by low pressure CVD process. After forming a desired resist pattern 10 by the photolithography technology, the phosphorus-doped polycrystal silicon is etched with the resist pattern 10 used as a mask, thereby forming a gate electrode 9.
Then as shown in FIG. 20, after removing the resist pattern 10, arsenic ions are implanted with a density of 4xc3x971015/cm2 at an energy of 50 KeV by ion implantation process, thereby to form an impurity-doped layer 11 of a conductivity type different from that of the silicon substrate 1. Then heat treatment is applied in nitrogen atmosphere at 800xc2x0 C. for about 30 minutes, thereby to form an N-type diffusion layer 11 which is an impurity-doped layer by activating the arsenic ions. Thus an MOS (Metal Oxide Semiconductor) transistor 40 comprising the gate oxidation film 8, the gate electrode 9 and the impurity-doped layer 11 is formed.
Then as shown in FIG. 21, after depositing a silicon oxide film 12 having thickness of about 1000 xc3x85 by the CVD process, a boron phosphate glass 13 is deposited by the CVD process. After reflowing the boron phosphate glass 13 through heat treatment applied in nitrogen atmosphere at 850xc2x0 C. for 30 minutes, a resist pattern (not shown) is formed by photolithography technology. The resist pattern is used as a mask in etching the boron phosphate glass 13 and the silicon oxide film 12 to make contact holes (not shown), followed by deposition of an aluminum-silicon-copper (Alxe2x80x94Sixe2x80x94Cu) alloy film by a sputtering technique.
Then a resist (not shown) is applied in a desired pattern by the photolithography technology, and the resist pattern is used as a mask for etching the aluminum-silicon-copper alloy film, thereby to form an aluminum-silicon-copper wiring 14.
The semiconductor device of the prior art is constructed as described above, while semiconductor elements such as transistor are electrically isolated from each other by the trench isolation structure.
In the semiconductor device of the prior art described above, while the gate oxidation film 8 of the transistor is formed by thermal oxidation process after forming the trench isolation structure 30 as shown in FIG. 19, an oxidation agent tends to diffuse into the silicon oxide filling 7, which is embedded in the groove, 5 and react with the silicon of the substrate 1 included in the inner wall of the groove 5, resulting in the oxidation of the silicon included in the inner wall of the groove 5. That is, oxidation of silicon in the reaction of Si+O2xe2x86x92SiO2 causes silicon to turn into a silicon oxide film, while the volume increases with the ratio of silicon to silicon oxide being 1:2. In the present case, since the groove 5 is filled with the silicon oxide filling 7, the increased volume causes a compressive stress in the silicon located near the groove 5. The compressive stress causes crystalline defects to be generated in the silicon located near the groove 5.
FIG. 22 is a diagram for explaining a mechanism wherein leak current flowing through an NP junction between an N-type diffusion layer (drain) 11a and a Pxe2x88x92type silicon substrate 1 increases due to the generation of crystalline defects in the silicon located near the groove 5. In FIG. 22, when an N type diffusion layer (source) 11b and the Pxe2x88x92type silicon substrate 1 are grounded with a voltage of 3.3 V applied to the gate electrode 9 and 3.3 V applied to the drain lla to operate the MOS transistor, a depletion layer 19 is generated in the vicinity of the interface between the drain 11a and the Pxe2x88x92type silicon substrate 1. At this time, in case there is crystalline defect 20 caused by the stress due to formation of the groove 5 in the silicon substrate 1, the depletion layer 19 may involve the crystalline defect 20 where electron-hole (21-22) pairs are generated, thereby increasing the leak current flowing through the NP junction between the drain 11a and the Pxe2x88x92type silicon substrate 1.
In the semiconductor device which employs the trench isolation structure of the prior art, as described above, there has been such a problem that the stress, caused by volume expansion through the oxidation of the silicon after forming the trench isolation structure, thereby increasing junction leak current and consequently causing an increased current consumption in the semiconductor device.
The present invention has been attained to solve the problem described above, and an object of the present invention is to provide a semiconductor device wherein the current consumption is reduced by controlling the generation of crystalline defects, and another object of the present invention is to provide a method of producing the semiconductor device.
A semiconductor device of the first invention is a semiconductor device having a plurality of transistors comprising a semiconductor substrate of first conductivity type having a principal plane, a gate electrode formed on the principal plane via a gate oxidation film and impurity-doped layers of the second conductivity type formed on the principal plane on both sides of the gate electrode, wherein the plurality of transistors are isolated from each other by filling a groove formed by etching the semiconductor substrate with an insulating material, while a nitride layer is provided by nitriding the semiconductor in the inner surface of the groove.
A semiconductor device of the second invention is that wherein the nitride layer is formed by a nitriding treatment using a nitrogen monoxide gas.
A semiconductor device of the third invention is a semiconductor device, wherein the nitriding treatment is carried out at a temperature of not less than 800xc2x0 C.
A semiconductor device of the fourth invention is a semiconductor device, wherein the nitriding treatment is carried out by using an ammonia gas.
A semiconductor device of the fifth invention is a semiconductor device, wherein the nitriding treatment carried out at a temperature of not less than 700xc2x0 C.
A method of producing the semiconductor device according to the sixth invention is a method of producing the semiconductor device having a plurality of transistors comprising a semiconductor substrate of first conductivity type having a principal plane, a gate electrode formed on the principal plane via a gate oxidation film and impurity-doped layers of the second conductivity type formed on the principal plane on both sides of the gate electrode, wherein a step of isolating the plurality of transistors from each other comprises a step of forming a groove by etching the semiconductor substrate, a step of nitriding the semiconductor of the inner surface of the groove thereby to form a nitride layer, and a step of filling the groove with an insulating material.
A method of producing the semiconductor device according to the seventh invention is a method, wherein the step of forming the nitride layer comprises a step of carrying out the nitriding treatment using a nitrogen monoxide gas.
A method of producing the semiconductor device according to the eighth invention is a method, wherein the nitriding treatment is carried out at a temperature of not less than 800xc2x0 C.
A method of producing the semiconductor device according to the ninth invention is a method, wherein the step of forming the nitride layer comprises a step of nitriding treatment carried out by using an ammonia gas.
A method of producing the semiconductor device according to the tenth invention is a method, wherein the nitriding treatment is carried out at a temperature of not less than 700xc2x0 C.
The present invention, having the configuration described above, provides the following effects.
According to the first and the sixth inventions, since the plurality of transistors are isolated from each other and the nitride layer is formed on the inner surface of the groove which constitutes the trench isolation structure, expansion of the oxide film due to the oxidation treatment after filling the groove is suppressed thereby preventing crystalline defects from being generated due to the compressive stress generated in the semiconductor substrate, thus minimizing the leak current caused by crystalline defect and improving the characteristics of the junction, and therefore it is made possible to produce the semiconductor device of low power consumption and stable operation.
Further according to the second and the seventh inventions, the nitriding treatment can also be effectively performed from above the insulating material in which case nitrogen gas concentrates to the interface between the semiconductor substrate and the insulating material due to diffusion, thus forming a strong oxidation control layer.
Also according to the third and the eighth inventions, the nitride layer having sufficient oxidation control effect can be formed by applying the nitriding treatment with the nitrogen monoxide gas at a temperature of 800xc2x0 C. or higher.
Further according to the fourth and the ninth inventions, ammonia gas can be applied from above the insulating material for the nitriding treatment in which case nitrogen concentrates to the interface between the semiconductor substrate and the insulating material due to diffusion, thus forming a strong oxidation control layer.
Also according to the fifth and the tenth inventions, the nitride layer having sufficient oxidation control effect can be formed by applying the nitriding treatment using ammonia gas at a temperature of 700xc2x0 C. or higher.